1. Technical Field
The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly, to a storage electrode of a capacitor of a semiconductor device and a method of forming a storage electrode of a capacitor.
2. Discussion of Related Art
A DRAM device generally includes a cell array composed of cells to store information, and a peripheral circuit to transfer the information to an exterior region. A memory cell of the DRAM device is generally composed of a transistor for a switching function, and a capacitor for storing information. Hence, an important factor in a DRAM semiconductor device is a capacitance of the cell capacitor for storing information. In this respect, providing a capacitor having a maximized capacitance with a small area is important in the fabrication of the DRAM device that has a reduced minimum line width and high integration.
A capacitance of a capacitor is proportional to the permittivity of its dielectric layer and the area of its electrodes. The capacitor is also inversely proportional to the interval between the capacitor's electrodes. So one way to maximize the capacitance is to increase the areas of the capacitor's electrodes, reduce an interval between the capacitor's electrodes, and use a material layer having a high permittivity for the capacitor's dielectrics.
A bridge may result between storage electrodes (lower electrodes) of different cells due to procedure misalignment and lack of process margins. This problem is a manifestation of a reduced design rule with a highly integrated DRAM device. The bridge may cause twin bit or multi-bit failures. Specifically, the magnitude of the bridge problem in a stack cell structure is inversely proportional to the interval between the storage electrodes (lower electrodes). That is, if the interval is increased, the number of bridges will decrease. But then surface areas of the storage electrodes (lower electrodes) are reduced, and thus, a capacitance of a capacitor is reduced.
Recently, methods proposed to solve the bridge problem include a concave capacitance structure. The concave structure is divided into a box type and a cylinder type.
FIGS. 1 to 4 are cross-sectional views illustrating processes of a conventional method of forming a storage electrode of a concave structure capacitor.
Referring to FIG. 1, an insulating layer 102 is formed on a semiconductor substrate 100 having an isolation layer (not shown) and a transistor (not shown) formed thereon. The insulating layer 102 may be a silicon oxide layer, a silicon oxynitride layer, a phosphosilicate glass (PSG) layer, an undoped silicate glass (USG) layer, a borophosphosilicate glass (BPSG) layer, a plasma enhanced tetraethylothosilicate glass (PE-TEOS) layer, a TEOS layer, or a combination of these layers. Then, a contact plug 104 is formed to penetrate the insulating layer 102 and to contact with a source region (not shown) of the transistor. Then, a lower mold layer 106, an etch stop layer 108, and an upper mold layer 110 are formed on the surface of the resultant structure including the contact plug 104. The upper mold layer 110 is formed of a silicon oxide layer, and is formed of a material layer having a high etch rate in an oxide layer etch recipe, such as for a P-TEOS or SOG group. Then, the upper mold layer 110, the etch stop layer 108, and the lower mold layer 106 are sequentially patterned, forming a storage electrode hole 112 exposing the contact plug 104.
Referring to FIG. 2, a storage electrode layer 116 and a sacrificial layer such as a sacrificial oxide layer 118 are formed on the surface of the resultant structure including the storage electrode hole 112. The storage electrode layer may be a metal layer and a metal nitride layer. The metal layer may be a titanium layer. The metal nitride layer may be a titanium nitride layer. The sacrificial oxide layer 118 may be a silicon oxide layer, a silicon oxynitride layer, a PSG layer, a BSG layer, a BPSG layer, a TEOS layer, a PE-TEOS layer, a spin-on-glass (SOG) layer, a photosensitive layer, or a combination of these layers.
Here, a thin TiSix layer (for example, TiSi2 layer) 117 is formed between the storage electrode layer 116 and the contact plug 104 during the formation of the storage electrode layer 116, to increase adhesiveness between the storage electrode layer 116 and the contact plug 104.
Referring to FIG. 3, after the sacrificial oxide layer 118, which buries the storage electrode hole 112, is formed, a node separation process for the storage electrodes is performed. First, the sacrificial oxide layer 118 and the storage electrode layer 116 are planarized and etched until the upper mold layer 110 is exposed, separating a storage electrode 116s into a cell unit. The storage electrode 116s is a cylinder type or a box type, depending on the shape of the storage electrode layer 116. That is, the storage electrode layer 116 fully filling the storage electrode hole 112 forms the storage electrode 116s having a box structure, and the storage electrode layer 116 conformally covering the inner wall of the storage electrode hole 112 forms the storage electrode 116s having a cylinder structure. Then, the sacrificial oxide layer 118 remaining inside the cylinder of the cylinder-structured storage electrode 116s is removed using a wet etch process, to expose the inner wall of the storage electrode 116s. 
Referring to FIG. 4, the upper mold layer 110 is isotropically etched, thereby exposing the etch stop layer 108, and concurrently, exposing the outer wall of the storage electrode 116s. 
Then, subsequent processes of forming a capacitor are performed such as conformally forming a capacitor dielectric layer 120 on the surface of the resultant structure in which the outer wall of the storage electrode 116s is exposed.
FIGS. 5 to 8 are views illustrating a problem generated in the conventional method of forming a storage electrode of a capacitor.
Referring to FIGS. 5 to 8, the sacrificial oxide layer 118 remaining inside the cylinder of the cylinder-structured storage electrode 116s is removed using a wet etch process. Further, after the storage electrodes 116s are separated into a cell unit, the upper mold layer 110 (FIG. 3) surrounding the storage electrode 116s is removed by an isotropic etching using a wet etch process.
While either the sacrificial oxide layer 118 inside the cylinder of the storage electrode 116s or the upper mold layer 110 is removed using a wet etching, an etch solution may penetrate into the grain boundary of the storage electrode 116s, to reach the TiSix layer (for example, TiSi2 layer) 117, and etch the TiSix layer (for example, TiSi2 layer) 117.
Further, the etch solution may penetrate into the lower mold layer 106 existing below the etch stop layer 108 through the interface between the storage electrode 116s and the etch stop layer 108, to etch the lower mold layer 106.
Then, the etch solution penetrates into the storage electrode 116s, and there occurs a Galvanic reaction between the storage electrode 116s and the contact plug 104. The contact plug 104 partially corrodes so that cavities are generated. The phenomenon brings snail-shaped defects, which may be so called ‘snail defect’ by one skilled in the art.
As shown in FIG. 6, a height of the storage electrode 116s is formed relatively high compared to its width, to maximize the capacitance of the capacitor within a limited area. Hence, the lower mold layer 106 functions to support the lower portion of the storage electrode 116s having a high aspect ratio. However, during the removal of the sacrificial oxide layer 118 and the upper mold layer 110, the lower mold layer 106 and the insulating layer 102 may be inadvertently etched by the penetrating etch solution. Then the storage electrode 116s may fall, causing a bridge to occur between neighboring storage electrodes 116s, thereby causing twin bit or multi-bit failures.
Further, the etching of the lower mold layer 106 and the insulating layer 102 during the operation of removing the sacrificial oxide layer 118 and the upper mold layer 110 may cause a lift-up phenomenon, wherein the storage electrode 116s lifts up from the lower mold layer 106 and the insulating layer 102, and the structure of the storage electrode 116s formed through the node separation process may be distorted during an operation of forming a capacitor dielectric layer or an operation of annealing the capacitor dielectric layer. That is, if the lower mold layer 106 and the insulating layer 102 are excessively etched during the operation of removing the sacrificial oxide layer 118 and the upper mold layer 110, the interfaces of the storage electrode 116s, the lower mold layer 106, and the insulating layer 102 may be completely separated, thereby causing a lift-up phenomenon, in which the storage electrode 116s is lifted up. The etch for the lower mold layer 106 and the insulating layer 102 during the operation of removing the sacrificial oxide layer 118 and the upper mold layer 110 is not excessive enough to cause the lift-up phenomenon. Even so, cavities may be generated by the etch of the lower mold layer 106 and the insulating layer 102, causing the structure of the storage electrode of the capacitor to be distorted during subsequent processes of forming a capacitor dielectric layer, or annealing the capacitor dielectric layer.
Further, with the degree of integration of semiconductor memory devices further increased in recent years, unit cell pitches have reduced. Hence, the thickness of the storage electrode 116s becomes even thinner. However, when the storage electrode 116s formed on the sidewall of the storage electrode hole 112 is further reduced in thickness, the etch solution used for removing the sacrificial oxide layer 118 penetrates more easily into the lower mold layer 106 and the insulating layer 102. Thus the problems described above are exacerbated.
FIGS. 7 and 8 are photographs illustrating the storage electrode of the capacitor in which the snail defect phenomenon occurs. FIG. 7 illustrates a leaning hole phenomenon caused by the inclined storage electrode, and FIG. 8 illustrates that cavities are generated in the lower mold layer due to the snail defect phenomenon.